1. Field of the Invention
The present invention relates to a continuity testing apparatus and a continuity testing method, and more particularly to a continuity testing apparatus and a continuity testing method for testing the condition of connection (or the condition of continuity) between a semiconductor device and a mounting substrate.
2. Description of Related Art
There has been known a technology in which a semiconductor device is internally provided with a circuit dedicated to connection checks, in order to check the condition of connection (or the condition of continuity) between the semiconductor device and a mounting substrate, after mounting of the semiconductor device on the mounting substrate. A NAND gate tree structure may be given as an example of the circuit dedicated to the connection checks, which is placed within the semiconductor device.
Patent document (U.S. Pat. No. 6,449,748) discloses a detection circuit including a NAND gate tree structure around a function circuit.
FIG. 6 is a diagram showing a configuration of the detection circuit according to Patent document. In FIG. 6, a NAND gate tree structure 200 is provided around a function circuit 202. Input terminals 23_0 to 23—n (where n denotes a positive integer) are to-be-tested terminals, while input terminals 206 are terminals not to be tested. In the NAND gate tree structure 200, NAND circuits are connected to the input terminals 23_0 to 23—n of the function circuit 202 on a one-to-one basis. One of two input signals to each of the NAND circuits is the corresponding one of the input terminals 23_0 to 23—n, while the other is an output signal from the NAND circuit in the preceding stage in the NAND gate tree structure 200.
An output signal 210 from each of NAND circuits 24_0 to 24—n is one of two input signals to the NAND circuit in the succeeding stage in the NAND gate tree structure 200. For example, the NAND circuit 24_1 receives, as inputs, output signals from the input terminal 23_1 and from the NAND circuit 24_0, while an output signal from the NAND circuit 24_1 is an input to the NAND circuit 24_2.
The NAND gate tree structure 200 is configured so that the output signal from the NAND circuit is received by a NAND circuit in the following stage (hereinafter, sometimes called a succeeding stage). Two input signals to the NAND circuit 24_0 located in the uppermost stage in a tree are the input terminal 23_0 and a power supply voltage VDD. Then, the detection circuit according to Patent document determines the condition of continuity, based on a voltage level of an output terminal 220 of the NAND circuit 24—n located in the lowermost stage in the tree.
FIG. 7 is a diagram showing the operation of the detection circuit according to Patent document, and a truth table showing a circuit operation. A NAND gate tree structure 702 includes NAND circuits D1 to D4 connected to each other through paths L1 to L3, and input terminals A to D. Inputs to the NAND circuit D1 are the input terminal A and the power supply voltage VDD. Inputs to the NAND circuit D2 are the input terminal B, and an output signal which propagates from the NAND circuit D1 through the path L1. Inputs to the NAND circuit D3 are the input terminal C, and an output signal which propagates from the NAND circuit D2 through the path L2. Inputs to the NAND circuit D4 are the input terminal D, and an output signal which propagates from the NAND circuit D3 through the path L3 and comes in.
Vectors in a truth table 704 showing the circuit operation of the NAND gate tree structure 702 shown in FIG. 7 are each formed of a pattern containing four input signals and one output signal. Description will be given for a method for detecting a break in the path L1, for example, of the NAND gate tree structure 702.
With the path L1 broken, an output from the NAND circuit D1 does not propagate into the NAND circuit D2 under any one of Vectors' 1st and 2nd conditions in the truth table 704. Thus, the NAND circuit D2 does not output a normal value, so that an output terminal OUT does not output an expected value. Under a Vector's 3rd condition, an input at the input terminal B is a “Lo (0)” level, and an output from the NAND circuit D3 is a “Hi (1)” level independently of an output from the NAND circuit D2. Consequently, the output terminal OUT outputs an expected value (because, with NAND logic, an output is always a “Hi (1)” level whenever the terminal B is at a “Lo (0)” level).
Under Vectors' 4th and 5th conditions, likewise, the output terminal OUT outputs their respective expected values. The break in the path L1 is detectable, based on the fact that abnormal conditions are encountered under the Vectors' 1st and 2nd conditions, whereas normal conditions are encountered under the Vectors' 3rd, 4th and 5th conditions.
FIG. 8 is a diagram showing a mounting evaluation environment according to Patent document. A test system 600 includes a function circuit 602 including the NAND gate tree structure 200 connected to the input terminals, shown in FIG. 6. The test system 600 includes a computer 604 that controls input of the patterns to the input terminals (or controls a pattern generator circuit), a pattern input/output interface 606, an evaluation substrate 608, and a test instrument 610 for testing a chip.